In a conventional nonvolatile semiconductor memory device (memory), elements are integrated in the two-dimensional plane on a silicon substrate. The dimension of one element is reduced (downscaled) to increase the storage capacity of the memory. However, such downscaling has recently become difficult in terms of cost and technology.
In this context, a collectively processed three-dimensional stacked memory has been proposed.
For instance, JP-A-2009-146954 discloses a technique for three-dimensionally arranging memory cells by forming memory holes in a stacked body in which a plurality of conductive layers functioning as control gates in the memory device are alternately stacked with insulating layers, forming a charge storage film on the inner wall of the memory hole, and then providing silicon in the memory hole. In this structure, the channel length along the stacking direction increases with the increase in the number of stacked layers.